IBM sub-1nm chip packs 100B transistors — can it extend Moore’s Law?

IBM has just done something the semiconductor industry thought was still years away: demonstrated a working chip technology that breaks the 1-nanometer barrier. The IBM sub-1nm chip, operating at a 0.7 nanometer node, isn’t just a smaller version of what came before. It represents a fundamentally different way of building transistors — and it could change what’s possible in AI computing, energy-efficient data centers, and consumer electronics for the next decade.

Key takeaways

• IBM has unveiled the world’s first sub-1 nanometer chip technology, operating at a 0.7 nm node using a new nanostack architecture.
• The chip packs nearly 100 billion transistors onto a surface the size of a fingernail by stacking them vertically in 3D layers.
• Compared to IBM’s 2 nm predecessor, the new design offers up to 50% higher performance or up to 70% greater energy efficiency.
• On-chip SRAM memory demonstrated 40% scaling, a key metric for AI workload support.
• This is a research milestone, not a commercial product — IBM estimates production could arrive within five years if the approach scales competitively.

IBM Announces the World’s First Sub-1 Nanometer Chip

The announcement landed on June 25, 2026, and it immediately raised the question that the chip industry has been quietly wrestling with for years: has Moore’s Law actually run out of road, or has someone just found a detour?

IBM’s answer, at least for now, is a detour — and a dramatic one. The 0.7 nm node is not an incremental step. It crosses a threshold that many engineers considered the practical limit of silicon transistor scaling. To get there, IBM didn’t just make transistors smaller in the traditional sense. It rebuilt the entire architecture from the ground up.

Breakthrough 0.7 nm Node Technology

The current industry standard sits around 2 nanometers — already mind-bendingly small, roughly the width of a few atoms. IBM’s new technology clocks in at 0.7 nm, making it the world’s first known chip technology below the 1-nanometer mark. To put that in perspective: a nanometer is a billionth of a meter, and transistors at this scale are operating at the boundary of what classical physics comfortably allows.

Jay Gambetta, Director of IBM Research and an IBM Fellow, called it “a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms.” His words carry weight — IBM has a long track record of semiconductor firsts, and the research community takes these announcements seriously even when commercial timelines remain uncertain.

Nanostack Architecture and 3D Transistor Stacking

The secret behind the breakthrough is what IBM calls the nanostack architecture — the industry’s first three-dimensional nanosheet-based transistor design. Rather than continuing to shrink transistors across a flat, two-dimensional plane (the approach that has driven chip progress for decades), IBM stacks and staggers them vertically in 3D layers using a technique called 3D sequential integration.

Professor Alan Woodward, a computer scientist at Surrey University, offered an accessible comparison: if existing 3D chip efforts from rivals like Samsung and Intel are the equivalent of 30 to 50-storey buildings, IBM’s NanoStack proposal is like a 100-storey skyscraper. “I think it’s fair to say IBM’s proposals are the most ambitious,” he said.

That ambition comes with real engineering challenges. Heat is a significant concern — transistors generate it as they switch, and in dense vertical stacks, that heat has nowhere easy to go. There are also issues around layer separation: if the insulating layers between transistors are too thin, the transistors can fail to switch off correctly. IBM’s ability to navigate these issues at volume will define whether this technology actually reaches production.

Technical Advancements and Performance Metrics

The headline numbers are striking by any measure.

Transistor Density and Chip Size

The nanostack design fits nearly 100 billion transistors on a chip roughly the size of a human fingernail. That density is made possible by going vertical — stacking layers that a conventional flat design simply couldn’t accommodate at this scale.

Performance and Energy Efficiency Gains

Against IBM’s own 2 nm predecessor, the 0.7 nm chip delivers up to 50% higher performance or, alternatively, up to 70% greater energy efficiency running equivalent workloads. The framing of “performance or efficiency” is deliberate: chip designers can tune the same underlying architecture for raw speed or for lower power consumption depending on what the application demands.

That flexibility matters enormously right now. The generative AI boom has turned data center power consumption into one of the most pressing problems in the tech industry. Server farms are straining electrical grids and demanding industrial-scale cooling. A chip that delivers the same computational output for 70% less energy isn’t just a technical achievement — it’s a potential answer to a very expensive, very real infrastructure crisis.

SRAM Scaling for AI Workloads

Beyond raw processing power, IBM validated the nanostack approach with working CMOS inverters and demonstrated 40% scaling in SRAM — the fast on-chip memory that feeds data directly to the processor. For AI workloads, where models constantly pull enormous amounts of data from memory, faster and denser on-chip memory is as important as the transistor count itself. A 40% improvement in SRAM scaling at this node is a meaningful signal that the architecture works for the kinds of workloads that matter most right now.

Development, Production Outlook and Industry Collaboration

This technology is being developed at a leading research facility in Albany, New York, which is soon to house an ASML High-NA EUV lithography tool — the most advanced chip-printing machine currently available, capable of etching circuits at the precision this node demands. The availability and readiness of High-NA EUV equipment is itself a factor in how quickly this research can transition toward production.

Timeline for Production

IBM estimates that production could be viable within five years, provided the nanostack approach proves scalable and no competitor reaches this milestone first. That conditional framing is honest — scaling a research prototype to high-volume manufacturing is a completely different challenge from demonstrating it in a lab. The history of semiconductor development is full of impressive research breakthroughs that took longer than expected to become products, or never did.

Collaborative Partners

IBM isn’t pursuing this alone. Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions are all collaborating on the process development needed to turn nanostack into a manufacturable technology. These are major names in semiconductor equipment — their involvement signals that the industry ecosystem is taking this seriously, not treating it as a pure research curiosity.

What makes this collaboration significant is what it implies about manufacturability. Equipment partnerships at this stage suggest IBM is already thinking about the process engineering required for production, not just the physics of the device itself. Getting world-class equipment makers in the room early is exactly what a company does when it believes a research breakthrough has a credible path to commercialization.

Gambetta framed the architectural shift in broad terms: “With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.” If that reinvention holds up at production scale, it could extend Moore’s Law for at least another decade beyond what most analysts had penciled in — and reshape the economics of AI hardware in the process.

FAQ

What is the significance of IBM’s 0.7 nanometer chip?

It is the world’s first sub-1 nanometer chip technology, using a novel 3D nanostack architecture that enables dramatically higher transistor density — nearly 100 billion on a fingernail-sized chip — and improved energy efficiency compared to previous generations.

How does IBM’s nanostack architecture differ from traditional chip designs?

Instead of shrinking transistors across a flat, two-dimensional surface, IBM’s nanostack approach stacks and staggers them vertically in 3D layers using 3D sequential integration. This increases transistor density without relying solely on lateral miniaturization, which is approaching physical limits.

What performance improvements does IBM’s new chip offer compared to previous generation 2 nm chips?

The 0.7 nm chip offers up to 50% higher performance or up to 70% greater energy efficiency compared to IBM’s 2 nm predecessor, depending on how the architecture is configured for a given application.

When could IBM’s sub-1 nm chip technology be commercially produced?

IBM estimates that production could occur within five years, provided the nanostack technology proves scalable to high-volume manufacturing and remains competitive against advances from other semiconductor companies.

Article produced with the assistance of artificial intelligence and reviewed by the editorial team.